There exists a need to create electronic and electromechanical systems often comprising dozens to many thousands of interconnects between subassemblies or modules. Several to many of said subassemblies may require to be joined to provide a solution for the final assembly that includes electrical, thermal, optical, mechanical and other forms of transduction and communication and also provide stability and support for the total assembly.
In building complex multilayer electronic and electro-mechanical systems, particularly those of high complexity, and high value, there remain challenges in building said systems with sufficiently high yield and or low re-work to produce said systems economically. This is particularly true when providing such systems in low quantity or with substantial customization or when providing reconfigurability and re-use of the key subsystems or modules comprising the integrated system.
For example, the desktop computer industry approached a similar but larger volume problem since at least the 1980s by creating motherboards and computer daughter cards with standardized connectors where the card and motherboard could be electrically and mechanically joined by one plugging into arrayed connectors and then being mechanically fastened to a metal chassis, for example, by screws. By doing so, cards could be replaced if defective, swapped to change functionality, and even motherboards replaced as necessary. Such boards and cards may be viewed as functional modules of a desired computer system that could be produced and tested independently of the final integrated computer system. Favorable benefits included not only improved yield and decreased rework, but also reduction in size of the system by allowing the system to become compact in a 3D volume due to the perpendicular interconnect.
This problem however is less straightforward for systems where one or more of the size, complexity, integration, weight, performance, or cost of desired interconnection becomes a limiting factor to produce the desired system. Even cooling such systems, for example in the aforementioned desktop computer, can remain a challenge, since forced air by using multiple fans become a difficult method to remove heat from all locations necessary. Also, thermal conduction through heat pipes and thermal busses and ground planes make modularity a challenge.
One can imagine maintaining the benefits of modularity would be desirable as one scales down in feature size or dimensions and scales up in complexity, functionality, and performance. Indeed this challenge has largely been addressed in modern consumer electronics by increasingly providing the functionality desired within microchips using integrated circuit technology where the size of the device's constituent elements, such as transistors, capacitors, resistors, interconnect metallization, and so on, have substantial improvements in reduced size and increased performance over discrete components. This trend of pushing so much desired functionality into densely integrated chips which are often permanently attached, combined with a rapid obsolescence rate has made it almost commonplace to dispose of the system if it fails; repair is too complicated and/or the cost of such repair exceeds the value of the system.
Compare this situation to one where the value of the components or chips or modules are very high but one or more of the integration density, size, weight, yield, performance and price are limiting factors, such that rework and modularity are required. Add to this the inability for any single semiconductor technology to provide all the performance or functions desired, or there simply being added constraints that make it impractical to integrate all the functions intimately into a chip or wafer level process. For example, a microwave phased array requires many functions, levels of interconnect, routing and distribution of signals and power, and require sophisticated engineering for heat dissipation, particularly as frequency increases and the dimensions available decrease. The area it needs to consume is based on performance limitations of its transmit/receive elements, but are also limited by the frequencies/wavelengths of its operation. For example at lower frequencies like X or S band, the pitch of the needed antenna elements are on a large spacing such that a wafer-level phased array does not appear to make sense even if the performance of the electronic components needed for each element were not the limiting factor. If one needed high power at S band, semiconductor technologies like GaN integrated circuits may be able to provide it, but it would not be economic to waste the un-needed area required by the antenna element spacing for a monolithic semiconductor technology any more than it would make sense to provide the many functions of a computer motherboard through complete integration onto a large semiconductor wafer.
Still there is the desire to combine many complex functions for systems such as phased arrays or mm-wave power amplifiers into the minimum size, volume, and weight possible. For many high end and often low volume applications, for example satellite applications, there is also the desire to not compromise performance.
Previous art has outlined interconnect technologies that can provide the routing and distribution of power and signals from DC to many hundreds of GHz. For example the PolyStrata® technology (a 3D additive build technology) developed and being commercialized by Nuvotronics LLC, Radford Va., USA is one such technology. Its ability to produce multi-layer, low dispersion, high isolation, coaxial and waveguide interconnection, combined with its high thermal conduction and ability to integrate thermal pathways, as well as its ability to interconnect with minimal excess parasitics to monolithic microwave integrated circuits, RF and DC passive components, and antenna elements makes it an ideal integration medium, similar to the use of circuit board technology that has integrated chips and other components for electronic applications.
Still the cost, yield, and complexity of the desired components to produce systems that push the edge of the state of the art in electronics may be such that modularity and rework are necessary economically and practically to produce such desired systems. However solving the challenges of modularity and rework when size and performance and even mechanical requirements of the necessary interconnect remains unsolved. Currently microelectronics approaches similar commercial problems using methods such as chip-stacking technology, through-substrate vias, tiered wirebonds, and in some cases attempts to integrate more than one semiconductor technology onto a single wafer. While these approaches may solve certain problems in volume production for reduced size, weight, and interconnection, they are not technologies that readily lend themselves to lower volumes, particularly where it is desired to have relatively un-compromised performance, rework, or modularity.
A further problem in existing electronic and electromechanical systems relates to chip or component interconnects. For instance, traditionally a semiconductor circuit or MEMS device is formed on wafer and then diced or otherwise separated into chips. For example, a MMIC power amplifier circuit made on a GaAs wafer. The chip would be formed with metal pads for probing and bonding to connect to the chip. Typically the back surface of the chip would be connected to a heatsink and electrical ground plane and then the front surface containing the bond pads would be wedgebonded or wirebonded into a surrounding circuit; alternatively the chip may be connected to a leadframe of a chip package, or packaged or used otherwise as is known in the art. In all of these cases, metal connections made by fused small wires such as gold wires, or by solders, are used to electrically join the chip's bond pads typically located around a perimeter of a chip, to the rest of the circuit, or are connected to leads for example of a lead-frame, to package the circuit. In the electronics industry today, high value chips can often be packaged in a manner that they can be inserted and removed from a separately formed chip-socket, said socket typically disposed on a motherboard. The chip socket provides the electrical and sometimes the thermal interfaces to and from the packaged chip. An example of this is the CPU on computer motherboards. Because the CPU is often the most expensive component and because it is desirable to be able to replace it to upgrade or service the computer system, the chip is packaged in a way to work in conjunction with a partner socket, allowing the packaged chip to be removed and replaced—thereby maintaining and improving the serviceability, versatility, and lifetime of the computer system. It remains a desirable and unmet need to reduce the size, mass, and form factor of a chip interconnection system—while improving performance. The performance aspect becomes of increasing interest on its own as frequency of operation of function on the chip increases from several to tens to hundreds of GHz where all aspects of chip become increasingly critical such as material properties, interconnect dimensions, transmission line properties, and any transitions to and from the chip. Thus a chip often must be designed for a specific method of packaging it. For example standards are created using leadframes, bondwires, overmolds and so on. For high frequency applications, for example, the surface mount “quad flat no-lead” or QFN has emerged as a popular approach as a variant of the quad flat packages (QFP). Despite the method of packaging, high value chips must typically be tested before being packaged. It would be desirable to have a system where the bare chip does not need to be additionally packaged in any permanent manner and instead the “bare die” can be inserted and interconnected into the system and still readily be removed to be replaced, without reworking or removing interconnect features from the bare die applied during packaging or assembly. For example, it would be desirable to eliminate the interconnects to a chip that are typically intended to be permanent, such as wirebonds, wedgebonds, beamleads, solder bumps or adhesive layers.
The PolyStrata® technology by Nuvotronics (disclosed in U.S. Pat. Nos. 7,012,489, 7,148,772, 7,405,638, 7,948,335, 7,649,432, 7,656,256, 8,031,037, 7,755,174, and 7,898,356, the contents of which patents are incorporated herein by reference), for example, has addressed the ability to integrate independently fabricated standard connectors including microwave connectors. It also has demonstrated stacked and lateral interconnect through conventional means such as solder joints. Independently fabricated and integrated connectors have the disadvantage of consuming substantial volume, size and even weight compared to the dimensions of chips and PolyStrata® integration substrates. In addition when many such interconnections are needed, substantial joining force and size mismatch become a limiting factor, for example in connecting dozens or hundreds of RF and DC interconnects. As frequency scales to mm-wave and beyond, loss and mismatch also become greater problems. For example, some of those have been described by Nuvotronics in international patent application publication number WO/2013/010108 “Methods of fabricating electronic and mechanical structures,” the contents of which are incorporated herein by reference.
Alternatively direct PolyStrata® board to board stacking or lateral joining connections between the coaxial RF, DC, waveguide, or thermal pathways may be based on direct solder joints at transition regions typically of the edges or upper or lower surfaces. Those interconnections based on solder joints have the disadvantage of often requiring the reflow of the solder to ensure a stable DC and RF junction that for example can allow testing or use in the field. Such reflow on a small scale becomes a challenge as, in increasingly small areas, limiting the flow or wicking or capillary action of the solder—as well as maintaining a thermal solder reflow or bonding hierarchy that doesn't interfere with the attachment of nearby chips or other components or modules—becomes difficult to manage. Also solders in substantially small volumes become difficult to control compositionally due to mechanisms such as interdiffusion and consumption of noble metals and diffusion barriers that may be applied in the junction regions. Embrittlement of the joint are common issues from such problems. Exact height and position control also become a challenge when solder bumps or joints may be many 10's to 100's of microns in thickness even after reflow; meanwhile, an advantage present in a technology such as PolyStrata® technology is reproducibility and control of gaps and distances that may be on the order or several microns or less. A high degree of planarity may be crucial for making multiple micron-scale interconnections across large, multiple centimeter distances.